The Verification Process confirms that Design Synthesis has resulted in a physical architecture that satisfies the system requirements. Throughout a system’s life cycle, design solutions at all levels of the physical architecture are verified to meet specifications.
Definition: Verification is a test of a system to prove that it meets all its specified requirements at a particular stage of its development. (IEEE-STD-610)
Verification and Validation (V&V) Overview
Validation and Verification (V&V) are steps to determine if a system or component satisfies its operational and system-level requirements. V&V requirements are established during the course of a program to provide adequate direction for system engineers to gauge the progress of a program. Validation is a quality control process that determines if operational requirements are met for the overall system to meet to Initial Capabilities Document (ICD) and Capability Development Document (CDD). The analysis is a testing method primarily used in Validation. Verification is a quality control process that determines if a system meets its system-level requirements. Inspection and demonstration is the main testing method used in Verification.
Visit: Verification and Validation (V&V)
Chart: Verification Flow Chart
Verification Process Objectives
The objectives of the Verification process include using established criteria to conduct verification of the physical architecture from the lowest level up to the total system to ensure that cost, schedule, and performance requirements are satisfied with acceptable levels of risk. Further objectives include generating data (to confirm that system, subsystem, and lower-level items meet their specification requirements) and validating technologies that will be used in system design solutions. A method to verify each requirement must be established and recorded during requirements analysis and functional allocation activities.
Verification Process Steps
The three (3) steps in the verification process include: [1,2]
- Step 1: Planning
- Step 2: Execution
- Step 3: Reporting
Step 1: Verification Planning 
Verification planning is performed at each level of the system under development. The following activities describe the development of a verification plan:
- Verification Method and Level Assignments: Defines the relationships between the specified requirements method and level of verification. This activity typically yields a Verification Cross Reference Matrix for each level of the architecture and serves as the basis for the definition of the verification tasks. The level of verification is assigned consistent with the level of the requirement (e.g., system-level, subsystem level, etc.). Verification activities include Analysis, Inspection, Demonstration, and Test. (see below) Choice of verification methods must be considered an area of potential risk. The use of inappropriate methods can lead to inaccurate verification.
- Verification Task Definition: Defines all verification tasks with each task addressing one or more requirements. The ability to define good verification tasks requires the test engineer to have a sound understanding of how the system is expected to be used and its associated environments. An essential tool for the test engineer is to utilize the integrated architecture that consists of the requirements, functional and physical architectures. The functional architecture is used to support functional and performance test development and in combination with the physical architecture, a family of verification tasks is defined that will verify the functional, performance, and constraint requirements.
- Verification Configuration Definition: Defines the technical configuration, resources, including people, and environments needed to support a given verification task. This may also include hardware or software to simulate the external interfaces to the system to support a given test.
- Verification Scheduling: Defines the schedule for the performance of the verification tasks and determines which verification tasks are in sequence or in parallel and the enabling resources required for the execution of the verification tasks.
Typical Verification Methods
Typical verification methods use the following:
- Analysis – the use of mathematical modeling and analytical techniques to predict the compliance of a design to its requirements based on calculated data or data derived from lower-level component or subsystem testing. It is generally used when a physical prototype or product is not available or not cost-effective. The analysis includes the use of both modeling and simulation.
- Inspection – the visual examination of the system, component, or subsystem. It is generally used to verify physical design features or specific manufacturer identification,
- Demonstration – the use of the system, subsystem, or component operation to show that a requirement can be achieved by the system. It is generally used for a basic confirmation of performance capability and is differentiated from testing by the lack of detailed data gathering, or
- Test – the use of the system, subsystem, or component operation to obtain detailed data to verify performance or to provide sufficient information to verify performance through further analysis. Testing is the detailed quantifying method of verification it is ultimately required in order to verify the system design.
Step 2: Verification Execution 
The performance of a given verification task with supporting resources. The verification task results, whether from a test, analysis, inspection or simulation, are documented for compliance or non-compliance with data supporting the conclusion.
Step 3: Verification Reporting 
Reports the compiled results of the executed verification plan and verifies the materials employed in system solutions can be used in a safe and environmentally compliant manner.
- Verification can be viewed as the intersection of systems engineering and test and evaluation.
AcqLinks and References:
-  Defense Acquisition Guidebook (DAG) – Chapter 4
-  DAU Systems Engineering Fundamentals Guide
- Picture: Verification Flow Chart from Chapter 7 of DAU SE Fundamentals Guide